The invention relates to power amplifiers, and more particularly to linear power amplifiers.
Current and future digital mobile hand-held communication systems, particularly with code-division multiple access (CDMA), use high efficiency, high linearity, and low cost power amplifiers (PA) for hand held transmitters. Gallium arsenide (GaAs) based heterojunction bipolar transistors (HBT's) are a proven candidate due to their superior power characteristics even at low bias voltages with only a single power supply. In addition to high efficiency and good linearity, the power amplifiers should work at temperature extremes. A typical operating temperature range for a mobile phone is −30° to +85° C., which presents additional challenges for the power amplifier. Traditional bias circuit topologies are inefficient in the precise control of the quiescent bias and dynamic operating point especially at temperature extremes. Currently there are two popular on-chip DC bias approaches used to minimize amplifier temperature variations, namely (i) diode-bias and (ii) current-mirror techniques. The diode bias technique has good temperature compensation, but the diode draws current, which may be significant. The simple current mirrors do not track as well over temperature. For longer battery life many handset manufacturers also include a “smart” bias function so that they can operate the mobile telephones at lower backed off power with much lower standby current.
In addition to improved PA efficiency and bias circuitry, a third issue is to maintain an acceptable system-required amplifier gain with minimum number of power amplifier stages, because the PA also amplifies receive band noise power at the receive frequencies. The noise power interferes with a downlink signal in the handset's receiver and reduces the dynamic range of the receiver. A large number of stages produces stronger receive band noise. Therefore, a minimum number of PA stages is preferred.
Although HBT's enable more efficient linear RF power, practical implementation of these devices faces a number of reliability challenges. The classic destructive thermal runaway phenomenon that is known in silicon bipolar junction transistors (BJT) also exists in GaAs-based HBT's. Any bipolar device which is connected in parallel with other similar devices and which is hotter than its neighbors tends to draw more current, thus heating itself even more and eventually destroying the device. A classic circuit technique, which attempts to avoid this problem, is the use of an emitter ballast resistor, which is used in silicon BJT's. The drawback of this technique is that any voltage drop on the ballast resistor is wasted RF power and therefore reduces amplifier efficiency. Some prior art circuit techniques attempt to reduce the effect of the ballast resistor on output amplifier power by a shunt parallel capacitor, the so-called R/C ballasting and therefore improve efficiency.
To a first order, the power amplifier performance is defined by the performance of the single transistor unit cell. Therefore, an optimum unit cell design improves amplifier performance. The transistor combining is done in several levels of hierarchy. First, transistor unit cells are connected in parallel to form a transistor array (or a larger transistor cell). Second, the transistor arrays are again combined to form the final power transistor. In order to achieve high efficiency, the output power transistor (thus the unit cell) has high power gain at the operating frequency while maintaining amplifier stability. As the power amplifier is optimally matched at high power, a transistor of the transistor unit cell has the best maximum available gain. There are two main geometries for HBT unit cell used in the prior art: a stripe (rectangular) emitter geometry and a circular geometry. The advantages of the stripe geometry include high maximum gain and capability in connecting bases in parallel for a lower parasitic base resistance. The advantages of a circular HBT layout include low parasitic base resistance and capability of making a large emitter area per unit cell with the largest emitter perimeter per unit emitter area, and the higher maximum gain.
For power amplifiers that have many devices in parallel in order to obtain the required output power level, a common issue is not losing the amplifier gain and power through combining loss and thus resulting low efficiencies. A typical microwave circuit approach is to use a “tree” topology for splitting or combining the signal for the input or output such that there is an equal delay from the input to each transistor and to the output combination point. With a low loss dielectric like GaAs, the combining efficiency is good with this approach. However, at cellular and PCS frequencies, this would result in a very large die size because the wavelength of the signal is very long.